1. Field of the Invention
The present invention relates to a data processor. More particularly, the present invention relates to a data processor using indirect addressing of registers.
2. Description of the Related Art
Operation frequencies of data processors have been recently increased while access times to memories have been decreased. This situation increases a need for reducing in access times of memories.
A technique is widely used in which a part of a working set within data on a memory is stored in a register to thereby reduce an access time of a memory. However, this technique requires an increase in the number of the registers to reduce the memory access. The increase of the registers prolongs instruction words and thus increases the amount of accesses needed for executing the instructions. Hence, the conventional technique encounters a demerit from the viewpoints of the performance ability and the cost.
When data stored in a register is processed by a data processor, data conversion is often requested. FIG. 1 shows a typical process of executing an instruction accompanied by data conversion. The instruction is executed in the three phases: a pre-operation data conversion (S101), an operation (S102) and a post-operation data conversion (S103). The pre-operation conversion (S101) is composed of a register read (S111), a data conversion (S112) and a register write (S113). The operation (S102) is composed of a register read (S114), an operation (S115) and a register write (S116). The post-operation conversion (S103) is composed of a register read (S117), a data conversion (S118) and a register write (S119).
A process of executing an instruction includes instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF and data write WB.
The instruction fetch IF is an action for reading out an instruction word from a main memory and transiently storing the instruction word in an instruction register.
The instruction decode ID is an action for decoding the instruction word. At first, an operation is specified on the basis of the operation code in the instruction word, and then a pre-operation data conversion is specified, and a post-operation data conversion is specified. Furthermore, a register address specifying a register for storing the operation result is specified on the basis of the operand field(s) of the instruction word.
The instruction execution EX is an action for executing an operation on the operand data. The data forward DF is an action for forwarding the operation result to a buffer and transiently storing the operation result therein. The write WB is an action for writing the operation result stored in the buffer to the specified register of the register file.
Data processors are often pipelined to improve the processing ability. In such data processors, executions of instructions are overlapped to increase the effective operation speed.
FIG. 2 shows a typical pipelining technique. To execute an instruction, instruction fetch IF, instruction decode ID, instruction execution EX, e data forward DF, and the data write WB are sequentially executed.
To execute a next instruction, instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID for the previous instruction. Then, instruction decode ID for the next instruction is executed in parallel with the instruction execution EX for the previous instruction. Next, instruction execution EX for the next instruction is executed in parallel with the data forward DF of the previous instruction. And, data forward DF for the next instruction is then executed in parallel with the write WB for the previous instruction. Finally, data write WB for the next instruction is executed.
If the next instruction has a dependence on the previous instruction, the operation result obtained by the instruction execution EX for the previous instruction can be forwarded during the instruction decode ID for the next instruction word. As a result, each of the instruction words can be executed substantially in one clock cycle.
However, execution of an instruction that requests data conversion degrades the processing ability of pipelined data processors. FIG. 3 shows a process of executing an instruction requesting a pre-operation data conversion in a pipelined data processor. An instruction accompanied by the pre-operation data conversion is separated into a data conversion instruction and an operation instruction. Firstly, instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF, and data write WB are executed for the data conversion instruction.
Instruction fetch IF for the operation instruction is executed in parallel with the instruction execution EX for the data conversion instruction. This means one clock cycle is wasted. Instruction decode ID for the operation instruction is then executed in parallel with the data forward DF for the data conversion instruction, and instruction execution EX is executed in parallel with the data write WB for the previous instruction word. After that, data forward DF and data write WB are executed for the operation instruction.
To execute a next instruction, instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID of the operation instruction of the previous instruction. Instruction decode ID for the next instruction is then executed in parallel with the instruction execution EX for the operation instruction. Instruction execution EX for the next instruction is executed in parallel with the data forward DF for the operation instruction, and the data forward DF for the next instruction is executed in parallel with the data write WB for the operation instruction. After that, the data write WB for the next instruction is executed.
When the next instruction has a dependence on the previous instruction word, the operation result produced by the instruction execution EX for the operation instruction is forwarded during the instruction decode ID for the next instruction word. This implies that it takes three clock cycles for an instruction accompanied by the pre-operation data conversion to be executed.
FIG. 4 shows a process of executing an instruction accompanied by post-operation data conversion in a typical pipelined data processor. The instruction accompanied by the post-operation data conversion is separated into an operation instruction and a data conversion instruction. Instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF and data write WB are sequentially executed for the operation instruction.
The instruction fetch IF for the data conversion instruction is executed in parallel with the instruction decode ID for the operation instruction. The instruction decode ID is then executed in parallel with the instruction execution EX for the operation instruction, and then the instruction execution EX is executed in parallel with the data forward DF for the operation instruction. Next the data forward DF is executed in parallel with the data write WB for the operation instruction. Finally, the data write WB for the data conversion instruction is executed. The operation result produced by the instruction execution EX for the operation instruction word is forwarded during the instruction decode ID for the data conversion instruction.
To execute a next instruction, the instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID for the data conversion instruction. Next the instruction decode ID is executed in parallel with the instruction execution EX for the data conversion instruction, and then the instruction execution EX is executed in parallel with the data forward DF for the data conversion instruction. The data forward DF is then executed in parallel with the data write WB for the data conversion instruction. Finally, the data write WB for the next instruction is finally executed. It takes substantially two clock cycles for the instruction requesting data conversion after the operation to be executed.
When data conversion is requested in data processing, the conventional data processor requests a set of data conversion instructions that are respectively provided for possible data conversions, or requests a set of instructions respectively provided for available data types. Therefore, an increase in the number of available data types increases the number of instructions, and also increases the instruction word lengths of the instructions.
Moreover, in the conventional data processor, an instruction specifies a location of data to be processed and the data type thereof. Hence, the change in the number of the registers for storing data to be processed enforces the modification of the instruction set. This hinders the conventional data processor to have compatibility of the instruction architecture.
Nakatsuka et al discloses a data processor which may be related to the present invention in Japanese Laid Open Patent Application (JP-A-Heisei 10-11352) is disclosed. The conventional data processor executes indirect addressing to fetch data to be processed from a register. The conventional data processor has physical registers, the number of which is greater than that of the logical registers. When the conventional data processor fetches an instruction, the conventional data processor determines a relationship between logical registers and physical registers on the basis of the instruction to produce a register-addressing field that allows an access to an accessible range of the logical registers. And the conventional data processor executes an access to the physical register by using the register-addressing field.
Sawada discloses another data processor which may be related to the present invention in Japanese Open Laid Patent Application (Jp-A-Showa 58-40668). The other conventional data processor executes indirect addressing for a register that stores data. The indirect addressing is achieved by a register address register which stores an address identifying a location of the register where the data to be processed. The register address register is counted up or down when the register is selected to be access.
An object of the present invention is to provide an improved data processor and data processing method for increasing an operation speed thereof.
Another object of the present invention is to provide an improved data processor and data processing method for reducing the number of instructions used in the data processor.
Another object of the present invention is to provide a data processor and a data processing method for shortening a word length of instruction word used therein.
Still another object of the present invention is to provide a data processor and a data processing method for enabling to increase a number of registers while maintaining compatibility of instruction architecture.
In order to achieve an aspect of the present invention, a data processor is composed of a register file including a plurality of registers, a register pointer section including a plurality of register pointers, an instruction register, a data type converter unit, and a processing unit. The each of the registers in the register file stores therein an operand data. Each of the register pointers stores therein a register address and a data type of the operand data stored in the register specified by the register address. The instruction register fetches an instruction word. The instruction word includes an operation code and an operand field representative of a register pointer address used for addressing a selected one of the register pointers to thereby indirectly addressing a selected one of the registers. The data type converter unit executes a data conversion on the operand data stored in the selected one of the registers to produce a converted operand data, on the basis of the data type stored in the selected register pointer specified by the register pointer address. The processing unit executes an operation specified by the operation code on the converted operand data to produce an operation result.
The data conversion on the operand data is preferably achieved without using software.
The data conversion on the operand data and the operation on the converted operand data are preferably executed during the same clock cycle.
The instruction word may further include another operand field indicative of another register pointer address to thereby indirectly specify a target register from among the plurality of registers. In this case, the operation result is stored in the target register.
The data processor is preferably further composed of another data converter unit executing another data conversion on the operation result on the basis of the data type specified by the another register pointer address.
The other data conversion on the operation result is preferably achieved without using software.
When the register pointer section includes a plurality of register pointer arrays, each of which respectively including ones of the register pointers, it is preferable that the data processor is further composed of a register bank controller which activates one of the plurality of register pointer arrays on the basis of the instruction word.
In order to achieve another aspect of the present invention, a data processor is composed of a register file including a plurality of registers, a read register pointer section including a plurality of read register pointers, a write register pointer section including a plurality of write register pointers, an instruction register, a processor unit, and first and second data type converter units. Each of the registers in the register file stores therein an operand data. Each of the read register pointers stores therein a read register address and a data type of the operand data stored in the register specified by the read register address. Each of the write register pointers stores therein a write register address and a data type of the operand data stored in the register specified by the write register address. The instruction register fetches an instruction word. The instruction word includes an operation code, and first and second operand field. The first operand field is indicative of a read register pointer address used for addressing a read register pointer from among the plurality of read register pointers to thereby indirectly address a read register from among the plurality of registers. The second operant field is indicative of a write register pointer address used for addressing a write register pointer from among the plurality of write register pointers to thereby indirectly address a write register from among the plurality of registers. The first data type converter unit executes a data conversion on the operand data stored in the read register to produce a converted operand data on the basis of the data type specified by the read register pointer address. The processor unit executes an operation specified by the operation code on the converted operand data to produce an operation result. The second data type converter unit executes another data conversion on the operation result to produce a converted operation result on the basis of the data type specified by the write register pointer address. The converted operation result is stored in the write register.
In this case, the first operand field may be allowed to be used as the second operand field.